PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Table 6 – Production Test Interface Signals (31)
Pin Name Type
Pin
No.
Function
TA[0]
TA[1]
TA[2]
TA[3]
TA[4]
TA[5]
TA[6]
TA[7]
TA[8]
TA[9]
TA[10]
TA[11]
Input
G1
G2
F2
G4
E2
D2
B4
D6
B5
D7
B6
D8
The test mode address bus (TA[11:0]) selects
specific registers during production test
(PMCTEST set high) read and write accesses.
In normal operation (PMCTEST set low), these
signals should be grounded.
TA[12]/TR Input
S
B9
The test register select signal (TA[12]/TRS)
selects between normal and test mode register
accesses during production test (PMCTEST set
high). TRS is set high to select test registers
and is set low to select normal registers. In
normal operation (PMCTEST set low), this
signal should be grounded.
TRDB
TWRB
Input
Input
C8
The test mode read enable signal (TRDB) is set
low during FREEDM-84A672 register read
accesses during production test (PMCTEST set
high). The FREEDM-84A672 drives the test
data bus (TDAT[15:0]) with the contents of the
addressed register while TRDB is low. In normal
operation (PMCTEST set low), this signal should
be tied to logic 1.
The test mode write enable signal (TWRB) is set
low during FREEDM-84A672 register write
accesses during production test (PMCTEST set
high). The contents of the test data bus
(TDAT[15:0]) are clocked into the addressed
register on the rising edge of TWRB. In normal
operation (PMCTEST set low), this signal should
be tied to logic 1.
B8
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
PMC [ PMC-SIERRA, INC ]
