PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Pin Name
Type
Pin
No.
Function
RXDATA[0]
RXDATA[1]
RXDATA[2]
RXDATA[3]
RXDATA[4]
RXDATA[5]
RXDATA[6]
RXDATA[7]
RXDATA[8]
RXDATA[9]
RXDATA[10]
RXDATA[11]
RXDATA[12]
RXDATA[13]
RXDATA[14]
RXDATA[15]
Tristate AC25 The receive data signals (RXDATA[15:0])
Output
AB24 contain the receive Any-PHY packet interface
AA23 (APPI) data output by the FREEDM-84A672
AC26 when selected. Data is presented in big endian
AB25 format, i.e. the byte in RXDATA[15:8] was
AA24 received by the FREEDM-84A672 before the
Y23
AB26
Y24
W23
Y25
W24
Y26
W25
V24
U23
byte in RXDATA[7:0].
The first word of each data transfer (when RSX
is high) contains an address to identify the
device and channel associated with the data
being transferred. The 10 least significant bits
(RXDATA[9:0]) contain the channel number (0 to
671) and the 3 most significant bits
(RXDATA[15:13]) contain the device base
address. The second and any subsequent
words of each data transfer contain valid data.
The FREEDM-84A672 may be programmed to
overwrite RXDATA[7:0] of the final word of each
packet transfer (REOP is high) with the status of
packet reception when that packet is errored
(RERR is high). This status information is bit
mapped as follows:
RXDATA[0]=’1’ => channel FIFO overrun.
RXDATA[1]=’1’ => max. packet length violation.
RXDATA[2]=’1’ => FCS error.
RXDATA[3]=’1’ => non-octet aligned.
RXDATA[4]=’1’ => HDLC packet abort.
RXDATA[7:5]=”Xh” => Reserved.
The RXDATA[15:0] signals are tristated when
the FREEDM-84A672 device is not selected via
the RENB signal.
The RXDATA[15:0] signals are updated on the
rising edge of RXCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
26
PMC [ PMC-SIERRA, INC ]
