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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
updated and is reset on detection of a frame pulse from the SBI SIPO blocks.  
For unchannelised or unframed links, the time-slot counter is held reset.  
9.10.2 Priority Encoder  
The priority encoder monitors the line interfaces for requests and synchronises  
them to the SYSCLK timing domain. Requests are serviced on a fixed priority  
scheme where highest to lowest priority is assigned from the line interface  
attached to link 0 to that attached to link 83. Thus, simultaneous requests from  
link ‘m’ will be serviced ahead of link ‘n’, if m < n. The priority encoder selects  
the request from the link with the highest priority for service. When there are no  
pending requests, the priority encoder generates an idle cycle. In addition, once  
every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no  
requests are serviced. This cycle is used by the channel assigner upstream for  
CBI accesses to the channel provision RAM.  
9.10.3 Channel Assigner  
The channel assigner block determines the channel number of the request  
currently being processed. The block contains a 2688 word channel provision  
RAM. The address of the RAM is constructed from concatenating the link  
number and the time-slot number of the highest priority requester. The fields of  
each RAM word include the channel number and a time-slot enable flag. The  
time-slot enable flag labels the current time-slot as belonging to the channel  
indicted by the channel number field. For time-slots that are enabled, the  
channel assigner issues a request to the THDL672 block which responds with  
packet data within one byte period of the transmit stream.  
9.11 SBI Inserter and SIPO  
The SBI transmit circuitry consists of an SBI Insert block and three SBI Serial to  
Parallel Converter (SBI SIPO) blocks. Each SIPO block processes data for one  
of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI ADD  
BUS. It receives serial data on either 28 links running at T1/J1 rate, 21 links at  
E1 rate or a single link at DS-3 rate and converts it to an internal parallel bus  
format. The SBI Insert block receives data from the SIPO blocks in the internal  
format and transmits it on the SBI ADD BUS.  
The SIPO blocks generate the serial clocks for the TCAS672 and thus are able  
to control the rate at which data is transmitted on to the SBI. The SBI Insert  
block can command the SIPO blocks to speed up or slow down these clocks in  
response to justfication requests received on the SBI interface. The SBI Insert  
block also contains FIFO circuitry to compensate for short term variations in the  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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