PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
the free space is greater than the limit set by XFER[3:0]. The roamer also
decrements the end-of-packet count when the reader signals that it has passed
an end of a packet to the HDLC processor. If the HDLC is transmitting a packet
and the FIFO free space is greater than the free space trigger level and there are
no complete packets within the FIFO (end-of-packet count equal to zero), a per-
channel starving flag is set. The roamer searches the starving flags in a round-
robin fashion to decide which channel FIFO should make expedited data
requests to the TMAC672 block. If no starving flags are set, the roamer
searches the request flags in a round-robin fashion to decide which channel
FIFO should make regular data requests to the TMAC672 block. The roamer
informs the partial packet writer of the channel FIFO to process, the FIFO free
space and the type of request it should make. The writer sends a request for
data to the TMAC672 block and writes the response data to the channel FIFO
setting block full flags. The writer reports back to the roamer the number of
blocks and end-of-packets transferred. The maximum amount of data
transferred during one request is limited by a software programmable limit.
The configuration of the HDLC processor is accessed using indirect channel
read and write operations as well as indirect block read and write operations.
When an indirect operation is performed, the information is accessed from RAM
during a null clock cycle identified by the TCAS672 block. Writing new
provisioning data to a channel resets the entire state vector.
9.10 Transmit Channel Assigner
The Transmit Channel Assigner block (TCAS672) processes up to 672 channels.
Data for all channels is sourced from a single byte-serial stream from the
Transmit HDLC Controller / Partial Packet Buffer block (THDL672). The
TCAS672 demultiplexes the data and assigns each byte to any one of 84 links.
When sending data to the SBI SIPO blocks, each link may be configured to
support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed
traffic at T1/J1, E1 or DS-3 rates. When sending data to the TD outputs, links 0,
1 and 2 support unchannelised data at arbitary rates up to 51.84 Mbps. Each
link is independent and has its own associated clock.
The 84 TCAS links have a fixed relationship to the SPE and tributary numbers on
the SBI ADD BUS as shown in the following table.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
