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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
rate at which data is output by the TCAS672 and the rate at which it is  
transmitted on the SBI ADD BUS.  
The SBI Insert block may be configured to enable or disable transmission of  
individual triburaries on to the SBI ADD bus. Individual triburaries may also be  
configured to operate in framed or unframed mode.  
9.12 Performance Monitor  
The Performance Monitor block (PMON) contains four counters. The first two  
accumulate receive partial packet buffer FIFO overrun events and transmit partial  
packet buffer FIFO underflow events, respectively. The remaining two counters  
are software programmable to accumulate a variety of events, such as receive  
packet count, FCS error counts, etc. All counters saturate upon reaching  
maximum value. The accumulation logic consists of a counter and holding  
register pair. The counter is incremented when the associated event is detected.  
Writing to the FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and  
Accumulation Trigger register transfer the count to the corresponding holding  
register and clear the counter. The contents of the holding register is accessible  
via the PCI interface.  
9.13 JTAG Test Access Port Interface  
The JTAG Test Access Port block provides JTAG support for boundary scan. The  
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions  
are supported. The FREEDM-84P672 identification code is 073840CD  
hexadecimal.  
9.14 PCI Host Interface  
The FREEDM-84P672 supports two different normal mode register types as  
defined below:  
1. PCI Host Accessible registers (PA) – these registers can be accessed  
through the PCI Host interface.  
2. PCI Configuration registers (PC) – these register can only be accessed  
through the PCI Host interface during a PCI configuration cycle.  
The PCI registers are addressable on dword boundaries only. The PCI offset  
shown in the table below must be combined with a base address to form the PCI  
Interface address. The base address can be found in the FREEDM-84P672  
Memory Base Address register in the PCI Configuration memory space.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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