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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
SBI  
SBI  
TCAS  
SBI  
SBI  
TCAS  
Link  
No.  
SBI  
SBI  
TCAS  
Link  
No.  
SPE Trib.  
Link  
No.  
SPE Trib.  
SPE Trib.  
No.  
1
No.  
28  
No.  
2
No.  
28  
No.  
3
No.  
28  
81  
82  
83  
As shown in the table above, TCAS links 0, 1, and 2 are mapped to tributary 1 of  
SPEs 1, 2 and 3 respectively. These links may be configured to operate at DS-3  
rate. (They may also be configured to output data to the TD outputs at rates up  
to 51.84 Mbps.) For each of these high-speed links, the TCAS672 provides a six  
byte FIFO. For the remaining links (TCAS links 3 to 83, mapped to links 2 to 28  
of each SPE), the TCAS672 provides a single byte holding register. The  
TCAS672 performs parallel to serial conversion to form bit-serial streams which  
are passed to the SBI SIPO blocks. In the event where multiple links are in need  
of data, TCAS672 requests data from upstream blocks on a fixed priority basis  
with link 0 having the highest priority and link 83 the lowest.  
Links containing a T1/J1 or an E1 stream may be channelised. Data at each  
time-slot may be independently assigned to be sourced from a different channel.  
The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse  
signals generated by the SBI SIPO blocks. With knowledge of the transmit link  
and time-slot identity, the TCAS672 performs a table look-up to identify the  
channel from which a data byte is to be sourced.  
Links containing a DS-3 stream are unchannelised, in which case, all data bytes  
on the link belong to one channel. The TCAS672 performs a table look-up to  
identify the channel to which a data byte belongs using only the outgoing link  
identity, as no time-slots are associated with unchannelised links. Links may  
additionally be configured to operate in an unframed “clear channel” mode, in  
which case the FREEDM-84P672 will output HDLC data in all bit positions,  
including those normally reserved for framing information. Links so configured  
operate as unchannelised regardless of link rate and the TCAS672 performs a  
table lookup using only the link number to determine the associated channel.  
9.10.1 Line Interface  
There are 84 line interface blocks in the TCAS672. Each line interface block  
contains a bit counter, an 8-bit shift register and a holding register that, together,  
perform parallel to serial conversion. Whenever the shift register is updated, a  
request for service is sent to the priority encoder block. When acknowledged by  
the priority encoder, the line interface responds by writing the data into the  
holding register.  
To support channelised links, each line interface block contains a time-slot  
counter. The time-slot counter is incremented each time the shift register is  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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