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PM7384-BI 参数 Datasheet PDF下载

PM7384-BI图片预览
型号: PM7384-BI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理84P672 [FRAME ENGINE AND DATA LINK MANAGER 84P672]
分类和应用:
文件页数/大小: 358 页 / 2808 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7384 FREEDM-84P672  
DATA SHEET  
PMC-1990445  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 84P672  
Figure 15 – Partial Packet Buffer Structure  
Partial Packet  
Buffer RAM  
Block  
Pointer RAM  
16 bytes  
16 bytes  
16 bytes  
16 bytes  
XX  
0x03  
XX  
Block 0  
Block 1  
Block 2  
Block 3  
Block 0  
Block 1  
Block 2  
Block 3  
0xC8  
16 bytes  
16 bytes  
0x01  
XX  
Block 200  
Block 200  
Block 2047  
Block 2047  
The writer and reader determine empty and full FIFO conditions using flags.  
Each block in the partial packet buffer has an associated flag. The writer sets  
the flag after the block is written and the reader clears the flag after the block is  
read. The flags are initialized (cleared) when the block pointers are written using  
indirect block writes. The reader declares a channel FIFO under-run whenever it  
tries to read data from a block without a set flag.  
The FIFO algorithm of the partial packet buffer processor is based on per-  
channel software programmable transfer size and free space trigger level.  
Instead of tracking the number of full blocks in a channel FIFO, the processor  
tracks the number of empty blocks, called free space, as well as the number of  
end of packets stored in the FIFO. Recording the number of empty blocks  
instead of the number of full blocks reduces the amount of information the  
roamer must store in its state RAM.  
The partial packet roamer records the FIFO free space and end-of-packet count  
for all channel FIFOs. When the reader signals that a block has been read, the  
roamer increments the FIFO free space and sets a per-channel request flag if  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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