PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x5DC : SBI EXTRACT Parity Error Interrupt Reason
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
SPE[1]
SPE[0]
TRIB[4]
TRIB[3]
TRIB[2]
TRIB[1]
TRIB[0]
PERRI
0
1
0
0
0
0
1
0
This register provides information about the most recent parity error on the SBI
DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PERRI
When set PERRI indicates that an SBI parity error has been detected.
Reading the SBI EXTRACT Parity Error Interrupt Reason Register clears this
bit.
TRIB[4:0] and SPE[1:0]
The TRIB[4:0] and SPE[1:0] fields specify the SBI tributary for which a parity
error was detected. These fields are only valid when PERRI is set.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
277
PMC [ PMC-SIERRA, INC ]
