PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x68C : SBI INSERT Tributary RAM Indirect Access Address
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
SPE[1]
SPE[0]
TRIB[4]
TRIB[3]
TRIB[2]
TRIB[1]
TRIB[0]
0
0
0
0
0
0
0
0
This register provides the transmit SPE and link number used to access the SBI
INSERT tributary control configuration RAM.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
TRIB[4:0] and SPE[1:0]
The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the
control configuration RAM write or read operation will apply to. Legal values
for TRIB[4:0] are b’00001’ through b‘11100’. Legal values for SPE[1:0] are
b’01’ through b‘11’.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM-
84P672 device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
279
PMC [ PMC-SIERRA, INC ]
