PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x5D0 : SBI EXTRACT Tributary RAM Indirect Access Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 8
Bit 7
R/W
BUSY
X
Bit 6
Unused
XXH
to
Bit 2
Bit 1
Bit 0
R/W
R/W
RWB
Reserved
0
0
This register controls access the SBI EXTRACT tributary control configuration
RAM. Writing to this register triggers an indirect register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
Reserved:
The reserved bit must be set low for correct operation of the FREEDM-
84P672 device.
RWB
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the tributary control configuration RAM. Writing a
‘0’ to RWB triggers an indirect write operation. Data to be written is taken
from the SBI EXTRACT Tributary RAM Indirect Access Data Register.
Writing a ‘1’ to RWB triggers an indirect read operation. The data read can
be found in the SBI EXTRACT Tributary RAM Indirect Access Data Register.
BUSY
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when a write to the SBI EXTRACT Tributary RAM
Indirect Access Control Register triggers an indirect access and will stay high
until the access is complete. This register should be polled to determine
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
273
PMC [ PMC-SIERRA, INC ]
