PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x680 : SBI INSERT Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Reserved
Unused
Unused
Reserved
Reserved
Reserved
Unused
0
X
X
0
0
0
X
1
R/W
R/W
R/W
R/W
SBI_PAR_CTL
This register controls the operation of the SBI INSERT block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
SBI_PAR_CTL
The SBI_PAR_CTL bit is used to configure the Parity mode for generation of
the SBI parity signal, ADP as follows: When SBI_PAR_CTL is ’0’ parity is
even. When SBI_PAR_CTL is ‘1’ parity is odd.
Reserved:
The reserved bits must be set low for correct operation of the FREEDM-
84P672 device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
278
PMC [ PMC-SIERRA, INC ]
