PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x5C0 : SBI EXTRACT Control
Bit
Type
Function
Default
Bit 15
to
Unused
XXXXXXH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Reserved
Unused
Unused
Reserved
Reserved
0
X
X
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
Reserved
SBI_PERR_EN
SBI_PAR_CTL
This register controls the operation of the SBI EXTRACT block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
SBI_PAR_CTL
The SBI_PAR_CTL bit is used to configure the Parity mode for checking of
the SBI parity signal, DDP as follows: When SBI_PAR_CTL is ’0’ parity is
even. When SBI_PAR_CTL is ‘1’ parity is odd.
SBI_PERR_EN
The SBI_PERR_EN bit is used to enable SBI Parity Error interrupt
generation. When SBI_PERR_EN is ‘0’, SBI Parity Error Interrupts are
disabled. When SBI_PERR_EN is ‘1’, SBI Parity Error Interrupts are
enabled. In both cases the SBI Parity checker logic will update the SBI
EXTRACT Parity Error Interrupt Reason Register when a parity error occurs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
270
PMC [ PMC-SIERRA, INC ]
