PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 19 – SPE Type Configuration
SPEn_TYP[1:0] Link Configuration
00
01
10
11
28 T1/J1 links
21 E1 links
Single DS-3 link
Reserved
FCLK_FREQ[1:0]:
The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set
according to the following table, depending on the frequency chosen for the
FASTCLK input.
Table 20 – FASTCLK Frequency Selection
FCLK_FREQ[1:0] FASTCLK Frequency
00
01
10
11
51.84 MHz
44.928 MHz
Reserved
66 MHz
Reserved:
The reserved bits must be set low for correct operation of the FREEDM-
84P672 device.
PERM_DRV:
The Permanent Bus Driver selector bit (PERM_DRV) enables the FREEDM-
84P672 device to drive the SBI ADD BUS continously. When set to 1, the
FREEDM-84P672 will drive the bus and assert the AACTIVE output at all
times, provided that the ADETECT[1:0] inputs are both 0. When set to 0, the
FREEDM-84P672 will only drive the bus and assert AACTIVE when it has
data to send (and when ADETECT[1:0] are both 0). PERM_DRV should only
be set to 1 if the FREEDM-84P672 is the only device driving the SBI ADD bus
and it is desired to prevent the bus tristating.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
121
PMC [ PMC-SIERRA, INC ]
