PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
FCLK_FREQ[1:0]:
The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set
according to the following table, depending on the frequency chosen for the
FASTCLK input.
Table 18 – FASTCLK Frequency Selection
FCLK_FREQ[1:0] FASTCLK Frequency
00 51.84 MHz
01
44.928 MHz
10
11
Reserved
66 MHz
Reserved:
The reserved bits must be set low for correct operation of the FREEDM-
84P672 device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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