PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
masters. In the event of a system or parity error it is recommended that the
core device be reset unless the cause of the fault can be determined.
PONS_E:
The Report PERR on SERR enable (PONS_E) bit controls the source of
system errors. When set high all parity errors will be signaled to the host via
the SERRB output signal.
RPWTH[5:0]:
The Receive Packet Write Threshold bits (RPWTH[5:0]) controls the amount
of data in the write FIFO before the GPIC begins arbitrating for the bus. The
GPIC will begin requesting access to the PCI bus when the number of dwords
of packet data loaded by the RMAC672 reaches the threshold specified by
RPWTH[5:0].
If the FREEDM-32P672 is being operated with PCICLK at a higher frequency
than SYSCLK, RPWTH must be set to a value that ensures that the write
FIFO does not underflow due to data being read out of the FIFO faster than
data is written into the FIFO. It is recommended that RPWTH be set to a
value not less than
!
SYSCLKfreq.1
!
SYSCLKfreq.1
ꢀ
4 P
ꢀ
XFER ꢁ 1
ꢁ
ꢁ
1 ꢀ
ꢀ rg P
"
2
"
2
PCICLKfreq.
PCICLKfreq.
#
3
#
3
where rg is the minimum number of clock cycles in which GNTB can be
received after REQB has been asserted.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
124
PMC [ PMC-SIERRA, INC ]
