PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x048 : FREEDM-84P672 SBI DROP BUS Master Configuration
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXXH
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Reserved
0
0
0
0
0
0
0
0
0
0
FCLK_FREQ[1]
FCLK_FREQ[0]
SPE3_TYP[1]
SPE3_TYP[0]
SPE2_TYP[1]
SPE2_TYP[0]
SPE1_TYP[1]
SPE1_TYP[0]
This register controls configures the operation of the SBI DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
SPEn_TYP[1:0]:
The SPE type bits (SPEn_TYP[1:0]) determine the configuration of each of
the three Synchronous Payload Envelopes conveyed on the SBI DROP BUS,
according to the following table.
Table 17 – SPE Type Configuration
SPEn_TYP[1:0] Link Configuration
00
01
10
11
28 T1/J1 links
21 E1 links
Single DS-3 link
Reserved
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
118
PMC [ PMC-SIERRA, INC ]
