RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
significant bit of each time-slot is transmitted first (B1 in Figure 21). The least
significant bit of each time-slot is transmitted last (B8 in Figure 21). The TD[n] bit
(B8 of TS31) before the framing byte is the least significant bit of time-slot 31. In
Figure 21, the quiescent period is shown to be a low level on TCLK[n]. A high
level, effected by extending the high phase of bit B8 of time-slot 31, is equally
acceptable. In channelised E1 mode, TCLK[n] can only be gapped during the
framing byte. It must be active continuously at 2.048 MHz during all time-slot
bits. Time-slots that are not provisioned to belong to any channel (PROV bit in
the corresponding word of the transmit channel provision RAM in the TCAS256
block set low) transmit the contents of the Idle Time-slot Fill Data register.
Figure 21 – Channelised E1 Transmit Link Timing
TCLK[n]
B8
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
TS 1 TS 2
TD[n]
B6 B7
TS 31
B1
FAS / NFAS
12.5 Receive APPI Timing
The receive Any-PHY packet interface (APPI) timing is shown in Figure 22
through Figure 24. The FREEDM-32A256 device provides data to an external
controller using the receive APPI. The following discussion surrounding the
receive APPI functional timing assumes that multiple FREEDM-32A256 devices
share a single external controller. All Rx APPI signals are shared between the
FREEDM-32A256 devices.
Figure 22 – Receive APPI Timing (Normal Transfer)
RXCLK
RXADDR[2:0]
RPA
Dev 0
NULL
Dev 7
Dev 0
NULL
CH 2
Dev 6
Dev 7
NULL
Dev 4
Dev 6
NULL
D3
Dev 0
Dev 4
NULL
Dev 1
Dev 0
NULL
D4
Dev 3
Dev 1
NULL
D6
Dev 2
Dev 3
NULL
Dev 2
RENB
Dev 0
D1
Dev 0
RXDATA[15:0]
RVAL
D0
D2
D5
D7
RSX
REOP
RMOD
RERR
PROPRIETARY AND CONFIDENTIAL
193
PMC [ PMC-SIERRA, INC ]
