RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Figure 22 shows the transfer of an 8 word packet across the Rx APPI from
FREEDM-32A256 device 0, channel 2. In this example, seven FREEDM-32A256
devices are sharing the Rx APPI, with device 5 being the null address.
The data transfer begins when the external controller selects FREEDM-32A256
device 0 by placing that address on the RXADDR[2:0] inputs and setting RENB
high. The external controller sets RENB low in the next RXCLK cycle to
commence data transfer across the Rx APPI. The FREEDM-32A256 samples
RENB low and responds by asserting RSX two RXCLK cycles later. The start of
all burst data transfers is qualified with RSX and an in-band channel address on
RXDATA[15:0] to associate the data to follow with a HDLC channel.
During the cycle when D2 is placed on RXDATA[15:0], the external controller is
unable to accept any further data and sets RENB high. Two RXCLK cycles later,
the FREEDM-32A256 tristates the Rx APPI. The external controller may hold
RENB high for an indeterminate number of RXCLK cycles. The FREEDM-
32A256 will wait until the external controller returns RENB low. Because the
FREEDM-32A256 does not support interrupted data transfers on the Rx APPI,
the external controller must reselect FREEDM-32A256 device 0 or output a null
address during the clock cycle before it returns RENB low. However, while
RENB remains high, the address on the RXADDR[2:0] signals may change.
When the FREEDM-32A256 device 0 samples RENB low, it continues data
transfer by providing D4 on RXDATA[15:0]. Note that if D3 were the final word of
the packet (Status), in response to sampling REOP high, the external controller
does not have to reselect FREEDM-32A256 device 0. This is shown in Figure
25.
The FREEDM-32A256 will not pause burst data transfers across the Rx APPI.
The FREEDM-32A256 automatically deselects at the end of all burst data
transfers. The FREEDM-32A256 must be reselected before any further data will
be transferred across the Rx APPI.
The RVAL and REOP signals indicate the presence and end of valid packet data
respectively. The RERR and RMOD signals are only valid at the end of a packet
and are qualified with the REOP signal. When a packet is errored, the FREEDM-
32A256 may be programmed to overwrite RXDATA[7:0] in the final word of
packet transfer with status information indicating the cause of the error.
RXDATA[15:0] is not modified if a packet is error free.
The RXADDR[2:0] signals serve to poll FREEDM-32A256 devices as well as for
selection. During data transfer, the RXADDR[2:0] signals continue to poll the
FREEDM-32A256 devices sharing the Rx APPI. Polled results are returned on
PROPRIETARY AND CONFIDENTIAL
194
PMC [ PMC-SIERRA, INC ]
