RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
corresponding TCLK[n] quiescent. In Figure 19, bits B5 and B2 are shown to be
stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure
19, the quiescent period is shown to be a low level on TCLK[n]. A high level,
effected by extending the high phase of the previous valid bit, is also acceptable.
Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame
boundaries.
Figure 19 – Unchannelised Transmit Link Timing
TCLK[n]
B1 B2 B3 B4 B5
B6
B7 B8 B1 B2
TD[n]
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of
a channelised T1/J1 link is shown in Figure 20. The transmit data stream is a
T1/J1 frame with a single framing bit (F in Figure 20) followed by octet bound
time-slots 1 to 24. TCLK[n] is held quiescent during the framing bit. The most
significant bit of each time-slot is transmitted first (B1 in Figure 20). The least
significant bit of each time-slot is transmitted last (B8 in Figure 20). The TD[n] bit
(B8 of TS24) before the framing bit is the least significant bit of time-slot 24. In
Figure 20, the quiescent period is shown to be a low level on TCLK[n]. A high
level, effected by extending the high phase of bit B8 of time-slot TS24, is equally
acceptable. In channelised T1/J1 mode, TCLK[n] can only be gapped during the
framing bit. It must be active continuously at 1.544 MHz during all time-slot bits.
Time-slots that are not provisioned to belong to any channel (PROV bit in the
corresponding word of the transmit channel provision RAM in the TCAS256 block
set low) transmit the contents of the Idle Fill Time-slot Data register.
Figure 20 – Channelised T1/J1 Transmit Link Timing
TCLK[n]
B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3
TD[n]
TS 24
F
TS 1
TS 2
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of
a channelised E1 link is shown in Figure 21. The transmit data stream is an E1
frame with a singe framing byte (FAS/NFAS in Figure 21) followed by octet bound
time-slots 1 to 31. TCLK[n] is held quiescent during the framing byte. The most
PROPRIETARY AND CONFIDENTIAL
192
PMC [ PMC-SIERRA, INC ]
