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PM7383-PI 参数 Datasheet PDF下载

PM7383-PI图片预览
型号: PM7383-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
Figure 14 – Transmit 8.192 Mbps H-MVIP Link Timing  
TMV8DC  
(16 MHz)  
TMV8FPC  
(4 MHz)  
TFP8B  
TD[n]  
B8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B1  
TS 1  
TS 127  
TS 0  
The timing relationship of the transmit data clock (TMVCK[n]), data (TD[m],  
where 8n?m?8n+7) and frame pulse (TFPB[n]) signals of a link configured for  
2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 15.  
The FREEDM-32A256 samples TFPB[n] low on the falling edge of the  
corresponding TMVCK[n] and references this point as the start of the next frame.  
The FREEDM-32A256 updates the data provided on TD[m] on every second  
falling edge of the corresponding TMVCK[n] as indicated for bit 2 (B2) of time-slot  
0 (TS 0) in Figure 15. The first bit of the next frame is updated on TD[m] on the  
falling TMVCK[n] clock edge for which TFPB[n] is also sampled low. B1 is the  
most significant bit and B8 is the least significant bit of each octet. Time-slots  
that are not provisioned to belong to any channel (PROV bit in the corresponding  
word of the transmit channel provision RAM in the TCAS256 block set low)  
transmits the contents of the Idle Fill Time-slot Data register.  
Figure 15 – Transmit 2.048 Mbps H-MVIP Link Timing  
TMVCK[n]  
(4 MHz)  
TFPB[n]  
TD[m]  
B8  
TS 31  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B1  
TS 1  
TS 0  
PROPRIETARY AND CONFIDENTIAL  
189