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PM7383-PI 参数 Datasheet PDF下载

PM7383-PI图片预览
型号: PM7383-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
Figure 17 – Channelised T1/J1 Receive Link Timing  
RCLK[n]  
B7 B8 F B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3  
RD[n]  
TS 24  
TS 1  
TS 2  
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of  
a channelised E1 link is shown in Figure 18. The receive data stream is an E1  
frame with a singe framing byte (F1 to F8 in Figure 18) followed by octet bound  
time-slots 1 to 31. RCLK[n] is held quiescent during the framing byte. The RD[n]  
data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the  
framing byte is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS31)  
clocked in by the last rising edge of RLCLK[n] before the framing byte is the least  
significant bit of time-slot 31. In Figure 18, the quiescent period is shown to be a  
low level on RCLK[n]. A high level, effected by extending the high phase of bit  
B8 of time-slot TS31, is equally acceptable. In channelised E1 mode, RCLK[n]  
can only be gapped during the framing byte. It must be active continuously at  
2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the  
PROV bit in the corresponding word of the receive channel provision RAM in the  
RCAS256 block to low.  
Figure 18 – Channelised E1 Receive Link Timing  
RCLK[n]  
B8  
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4  
RD[n]  
B6 B7  
TS 31  
F1 F2 F3 F4 F5 F6 F7 F8  
FAS / NFAS  
TS 1  
TS 2  
12.4 Transmit non H-MVIP Link Timing  
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of  
a unchannelised link is shown in Figure 19. The transmit data is viewed as a  
contiguous serial stream. There is no concept of time-slots in an unchannelised  
link. Every eight bits are grouped together into a byte with arbitrary byte  
alignment. Octet data is transmitted from most significant bit (B1 in Figure 19)  
and ending with the least significant bit (B8 in Figure 19). Bits are updated on  
the falling edge of TCLK[n]. A transmit link may be stalled by holding the  
PROPRIETARY AND CONFIDENTIAL  
191