RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x010 : FREEDM-32A256 Master Link Activity Monitor
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TLGA[7]
TLGA[6]
TLGA[5]
TLGA[4]
TLGA[3]
TLGA[2]
TLGA[1]
TLGA[0]
RLGA[7]
RLGA[6]
RLGA[5]
RLGA[4]
RLGA[3]
RLGA[2]
RLGA[1]
RLGA[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides activity monitoring on FREEDM-32A256 receive and
transmit link inputs. When a monitored input makes a low to high transition, the
corresponding register bit is set high. The bit will remain high until this register is
read, at which point, all the bits in this register are cleared. A lack of transitions is
indicated by the corresponding register bit reading low. This register should be
read periodically to detect for stuck at conditions.
RLGA[0]:
The receive link group #0 active bit (RLGA[0]) monitors for transitions on the
RD[3:0] and RCLK[3:0]/RMVCK[0]/RMV8DC inputs. RLGA[0] is set high
when either:
1. Each of RD[3:0] has been sampled low and sampled high by rising
edges of the corresponding RCLK[3:0] inputs, or
PROPRIETARY AND CONFIDENTIAL
80
PMC [ PMC-SIERRA, INC ]
