RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x00C : FREEDM-32A256 Master Clock / Frame Pulse / BERT
Activity Monitor and Accumulation Trigger
Bit
Type
Function
Default
Bit 15
to
Unused
XH
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TXCLKA
RXCLKA
TFPA[3]
TFPA[2]
TFPA[1]
TFPA[0]
RFPA[3]
RFPA[2]
RFPA[1]
RFPA[0]
TFP8A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RFP8A
TBDA
SYSCLKA
This register provides activity monitoring on the FREEDM-32A256 system clock,
Any-PHY clocks, H-MVIP frame pulse and BERT port inputs. When a monitored
input makes a transition, the corresponding register bit is set high. The bit will
remain high until this register is read, at which point, all the bits in this register are
cleared. A lack of transitions is indicated by the corresponding register bit
reading low. This register should be read periodically to detect for stuck at
conditions.
Writing to this register delimits the accumulation intervals in the PMON
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
PROPRIETARY AND CONFIDENTIAL
77
PMC [ PMC-SIERRA, INC ]
