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PM7383 参数 Datasheet PDF下载

PM7383图片预览
型号: PM7383
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
high before the next data transfer can begin, and (2) the transfer of a packet  
which completes when TRDY is set low illustrating that although the packet has  
been completely transferred, the external controller must still wait until TRDY has  
been sampled high before the next data transfer can begin.  
The first data transfer is a single word packet for FREEDM-32A256 device 3,  
channel 0. The FREEDM-32A256 asserts TRDY high one TXCLK cycle after  
TSX is sampled high. The Tx APPI protocol dictates that the external controller  
must wait until TRDY is sampled high before beginning the next data transfer for  
FREEDM-32A256 device 5, channel 255. The external controller must hold the  
last valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that  
data is a don’t care. The FREEDM-32A256 tristates the TRDY signal one TXCLK  
cycle after it has been driven high.  
The second transfer is a three word packet which completes transfer in the same  
TXCLK cycle that TRDY is sampled low by the external controller. Again, the  
external controller must hold the last valid word on TXDATA[15:0] until TRDY is  
sampled high. In this case, that data is D2, the last word of the packet. The  
FREEDM-32A256 may drive TRDY low for an indeterminate number of TXCLK  
cycles. During this time, the external controller must wait and is not permitted to  
begin another burst data transfer until TRDY is sampled high. When the external  
controller samples TRDY high, the current burst transfer is deemed to be  
complete and the external controller may begin the next data transfer. The  
FREEDM-32A256 tristates the TRDY signal one TXCLK cycle after it has been  
driven high.  
Figure 28 – Transmit APPI Timing (Polling)  
TXCLK  
Dev 0  
CH 254  
Dev 1  
TXADDR[12:0]  
CH 55  
CH 0  
CH 8  
CH 0  
NULL  
CH 0  
CH 199  
NULL  
Dev 0  
CH 254  
Dev 1  
CH 0  
TPA1[0]  
TPA1[1]  
TPA1[2]  
CH 55  
HUNGRY  
OK  
CH 8  
STARVE  
OK  
CH 0  
HUNGRY  
OK  
CH 199  
STARVE  
UFLOW  
STARVE  
UFLOW  
HUNGRY  
OK  
STARVE  
OK  
Dev 0  
Dev 1  
CH 1  
TPA2[0]  
TPA2[1]  
TPA2[2]  
CH 56  
STARVE  
OK  
CH 1  
CH 255  
CH 9  
HUNGRY  
OK  
CH 1  
CH 200  
STARVE  
UFLOW  
HUNGRY STARVE  
OK UFLOW  
HUNGRY HUNGRY  
OK OK  
Polling is completely decoupled from device and channel selection on the Tx  
APPI. Accordingly, the TXADDR[12:0] signals continue to provide only a poll  
address for any of the FREEDM-32A256 devices sharing the Tx APPI. The most  
PROPRIETARY AND CONFIDENTIAL  
199