RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
the FREEDM-32A256 samples RENB low, it begins the next data transfer as
before.
Figure 24 – Receive APPI Timing (Optimal Reselection)
RXCLK
RXADDR[2:0]
RPA
Dev 0
NULL
Dev 7
Dev 0
NULL
CH 2
Dev 6
Dev 7
NULL
D1
NULL
D125
Dev 0
D126
NULL
D127
Dev 4
Dev 0
NULL
Dev 0
Dev 3
NULL
Dev 4
D128
RENB
Dev 0
RXDATA[15:0]
RVAL
D0
CH 2
RSX
REOP
RMOD
RERR
Figure 24 shows optimal bandwidth utilization across the Rx APPI.
With knowledge that the maximum burst data transfer (excluding channel
address prepend) is 256 bytes, i.e. 128 words, the external controller sets RENB
high when the 127th word (D126) is placed on RXDATA[15:0] in anticipation of the
end of a burst transfer. The FREEDM-32A256 completes the burst data transfer
and tristates the Rx APPI one RXCLK cycle after RENB is sampled high.
Because the burst data transfer is complete and RENB is immediately returned
low following selection, the FREEDM-32A256 immediately begins the next data
transfer following the single turn-around cycle.
The protocol dictates that at least one tristate turn-around cycle be inserted
between data transfers, even if the external controller is reselecting the same
FREEDM-32A256 device. In other words, Figure 24 shows the earliest possible
time that the external controller could have set RENB high to reselect FREEDM-
32A256 device 0.
Figure 25 – Receive APPI Timing (Boundary Condition)
RXCLK
RXADDR[2:0]
RPA
Dev 0
NULL
Dev 7
Dev 0
NULL
CH 2
Dev 6
Dev 7
NULL
D1
Dev 4
Dev 6
NULL
Dev 4
Dev 7
Dev 1
NULL
Dev 7
Dev 3
Dev 1
NULL
Dev 2
Dev 3
NULL
Dev 2
RENB
Dev 7
D8
RXDATA[15:0]
RVAL
D0
D2
D3
CH 1
D9
RSX
REOP
RMOD
RERR
PROPRIETARY AND CONFIDENTIAL
196
PMC [ PMC-SIERRA, INC ]
