RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
The start of all burst data transfers is qualified with the TSX signal and an in-band
channel address on TXDATA[15:0] to associate the data to follow with a HDLC
channel. The TEOP signal indicates the end of valid packet data. The TMOD
and TERR signals held low except at the end of a packet (TEOP set high).
The FREEDM-32A256 starts driving the TRDY signal one TXCLK cycle after TSX
is sampled high. Upon sampling the TRDY signal high, the external controller
completes the current burst data transfer. The FREEDM-32A256 tristates the
TRDY signal one TXCLK cycle after it has been driven high. This is the case for
the first burst data transfer in Figure 26. In the second burst data transfer, the
FREEDM-32A256 drives the TRDY signal low to indicate that the FIFOs in the
TAPI256 are full and no further data may be transferred. Upon sampling the
TRDY signal low, the external controller must hold the last valid word of data on
TXDATA[15:0]. The FREEDM-32A256 may drive TRDY low for an indeterminate
number of TXCLK cycles. During this time, the external controller must wait and
is not permitted to begin another burst data transfer until TRDY is sampled high.
When the TAPI256 has at least one empty FIFO, the FREEDM-32A256 drives
the TRDY signal high. Upon sampling the TRDY signal high, the external
controller completes the current burst data transfer. The FREEDM-32A256
tristates the TRDY signal one TXCLK cycle after it has been driven high.
The external controller must sample the TRDY signal high before it can begin the
next burst data transfer. This prevents the external controller from bombarding
the FREEDM-32A256 device with small packets and allows the FREEDM-
32A256 to perform the necessary house-keeping and clean-up associated with
the ending of burst data transfers. This protocol also ensures that transitions
between burst data transfers do not require any extra per channel storage,
thereby simplifying implementation of both the external controller and the
FREEDM-32A256 device. Figure 27 illustrates this condition.
Figure 27 – Transmit APPI Timing (Special Conditions)
TXCLK
TRDY
Dev 3
Dev 5
TXDATA[15:0]
TSX
CH 0
D0
CH 255
D0
D1
D2
CH 2
D0
TEOP
TMOD
TERR
Figure 27 shows two special conditions – (1) the transfer of a one word packet
illustrating how the external controller must wait until TRDY has been sampled
PROPRIETARY AND CONFIDENTIAL
198
PMC [ PMC-SIERRA, INC ]
