RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x608 : TAPI Indirect Channel Data Register
Bit
Type
Function
Default
Bit 15
R/W
PROV
0
Bit 14
to
Unused
XH
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BLEN[7]
BLEN[6]
BLEN[5]
BLEN[4]
BLEN[3]
BLEN[2]
BLEN[1]
BLEN[0]
0
0
0
0
0
0
0
0
The TAPI Indirect Channel Data Register contains data read from the TAPI256
channel provision RAM after an indirect read operation or data to be written to
channel provision RAM in an indirect write operation.
BLEN[7:0]:
The channel burst length (BLEN[7:0]) bits report the data transfer burst length
read from the TAPI256 channel provision RAM after an indirect read operation
has completed. The data transfer burst length specifies the length (in bytes,
less one) of burst data transfers on the transmit APPI which are not
terminated by the assertion of TEOP. The data transfer burst length can be
specified on a per-channel basis. The data transfer burst length to be written
to the channel provision RAM in an indirect write operation must be set up in
this register before triggering the write. BLEN[7:0] reflects the value written
until the completion of a subsequent indirect read operation.
PROV:
The indirect provision enable bit (PROV) reports the channel provision enable
flag read from the TAPI256 channel provision RAM after an indirect read
operation has completed. The provision enable flag to be written to the
TAPI256 channel provision RAM, in an indirect write operation, must be set
PROPRIETARY AND CONFIDENTIAL
157
PMC [ PMC-SIERRA, INC ]
