RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x18C – 0x1FC : RCAS Links #3 to #31 Configuration
Bit
Type
Function
Default
Bit 15
to
Unused
XXXXH
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
MODE[2]
MODE[1]
MODE[0]
0
0
0
This register configures operational modes of receive links #3 to #31.
MODE[2:0]:
The mode select bits (MODE[2:0]) configures the corresponding receive link.
Table 10 details this procedure. When link 4m (0?m?7) is configured for
operation in 8.192 Mbps H-MVIP mode (MODE[2:0]=”111”), data cannot be
received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and
4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation
of the RCAS256. From a channel assignment point of view in the RCAS256
(Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are
treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the
H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64
through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link
4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as time-
slots 0 through 31 of link 4m+3.
Table 10 – Receive Links #3 to #31 Configuration
MODE[2:0]
Link Configuration
000
001
010
011
100
101
110
111
Unchannelised
Channelised T1/J1 (24 time slots labeled 1-24)
Channelised E1 (31 time slots labeled 1-31)
2 Mbps H-MVIP (32 time slots labeled 0-31)
Reserved
Reserved
Reserved
8 Mbps H-MVIP (128 time slots mapped to time-
slots 0 through 31 of links 4m, 4m+1, 4m+2 and
4m+3)
PROPRIETARY AND CONFIDENTIAL
102
PMC [ PMC-SIERRA, INC ]
