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PM7383 参数 Datasheet PDF下载

PM7383图片预览
型号: PM7383
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32A256 [FRAME ENGINE AND DATA LINK MANAGER 32A256]
分类和应用:
文件页数/大小: 231 页 / 1917 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7383 FREEDM-32A256  
DATASHEET  
PMC-2010336  
ISSUE 1  
FRAME ENGINE AND DATA LINK MANAGER 32A256  
Register 0x108 : RCAS Framing Bit Threshold  
Bit  
Type  
Function  
Default  
Bit 15  
to  
Unused  
XXXH  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
FTHRES[6]  
FTHRES[5]  
FTHRES[4]  
FTHRES[3]  
FTHRES[2]  
FTHRES[1]  
FTHRES[0]  
0
1
0
0
1
0
1
This register contains the threshold used by the clock activity monitor to detect  
for framing bits/bytes.  
FTHRES[6:0]:  
The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by  
the clock activity monitor to detect for the presence of framing bits. A counter  
in the clock activity monitor of each receive link increments on each rising  
edge of SYSCLK and is cleared, when the BSYNC bit of that link is set low,  
by each rising edge of the corresponding RCLK[n]. When the BSYNC bit of  
that link is set high, the counter is cleared at every fourth rising edge of the  
corresponding RCLK[n]. When the counter exceeds the threshold given by  
FTHRES[6:0], a framing bit/byte has been detected.  
FTHRES[6:0] should be set as a function of the SYSCLK period and the  
expected gapping width of RCLK[n] during data bits and during framing  
bits/bytes. Legal range of FTHRESH[6:0] is ‘b0000001 to ‘b1111110.  
Note: For operation with T1/J1 links and SYSCLK = 45 MHz, FTHRESH[6:0]  
should be set to ‘b0100101’. The default value of this register reflects this  
mode of operation.  
PROPRIETARY AND CONFIDENTIAL  
98