RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 9 – Receive Links #0 to #2 Configuration
MODE[2:0]
Link Configuration
000
001
010
011
100
101
110
111
Unchannelised
Channelised T1/J1 (24 time slots labeled 1-24)
Channelised E1 (31 time slots labeled 1-31)
2 Mbps H-MVIP (32 time slots labeled 0-31)
Reserved
Reserved
Reserved
8 Mbps H-MVIP (128 time slots mapped to time-
slots 0 through 31 of links 4m, 4m+1, 4m+2 and
4m+3)
BSYNC:
The byte synchronization enable bit (BSYNC) controls the interpretation of
gaps in RCLK[n] when link #n is in unchannelised mode (MODE[2:0]=”000”).
When BSYNC is set high, the data bit on RD[n] clocked in by the first rising
edge of RCLK[n] after an extended quiescent period is considered to be the
most significant bit of a data byte. When BSYNC is set low, gaps in RCLK[n]
carry no special significance. BSYNC is ignored when MODE[2:0]U”000”.
PROPRIETARY AND CONFIDENTIAL
101
PMC [ PMC-SIERRA, INC ]
