RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
PCI Offset
Register
0x480 - 0x4FC TCAS Link #0 through #31 Configuration
0x500
0x504
0x508
0x50C
0x510
PMON Status
PMON Receive FIFO Overflow Count
PMON Transmit FIFO Underflow Count
PMON Configurable Count #1
PMON Configurable Count #2
0x514 - 0x51C PMON Reserved
0x520 - 0x7FC Reserved
The following PCI configuration registers are implemented by the PCI Interface.
These registers can only be accessed when the PCI Interface is a target and a
configuration cycle is in progress as indicated using the IDSEL input.
Table 13 – PCI Configuration Register Memory Map
PCI Offset
Register
0x00
0x04
Vendor Identification/Device Identification
Command/Status
0x08
0x0C
0x10
0x14 - 0x24
0x28 - 0x38
0x3C
Revision Identifier/Class Code
Cache Line Size/Latency Timer/Header Type/BIST
CBI Memory Base Address Register
Unused Base Address Register
Reserved
Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
88
PMC [ PMC-SIERRA, INC ]
