RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
10
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
FREEDM-32P672.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2. Except where noted, all configuration bits that can be written into can also be
read back. This allows the processor controlling the FREEDM-32P672 to
determine the programming state of the block.
3. Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect
FREEDM-32P672 operation unless otherwise noted.
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the FREEDM-
32P672 operates as intended, reserved register bits must only be written with
their default values. Similarly, writing to reserved registers should be
avoided.
10.1 PCI Host Accessible Registers
PCI host accessible registers can be accessed by the PCI host. For each
register description below, the hexadecimal register number indicates the PCI
offset from the base address in the FREEDM-32P672 CBI Register Base
Address Register when accesses are made using the PCI Host Port.
Note
These registers are not byte addressable. Writing to any one of these registers
modifies all the bits in the register. Byte selection using byte enable signals
(CBEB[3:0]) are not implemented. However, when all four byte enables are
negated, no access is made to the register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
89