RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x004 : FREEDM-32P672 Master Interrupt Enable
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TFUDRE
IOCE
TDFQEE
TDQRDYE
TDQFE
RPDRQEE
RPDFQEE
RPQRDYE
RPQLFE
RPQSFE
RFOVRE
RPFEE
RABRTE
RFCSEE
PERRE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SERRE
This register provides interrupt enables for various events detected or initiated by
the FREEDM-32P672.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
91
PMC [ PMC-SIERRA, INC ]
