RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x080 : GPIC Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXH
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
RPWTH[5]
RPWTH[4]
RPWTH[3]
RPWTH[2]
RPWTH[1]
RPWTH[0]
Unused
Unused
Unused
Unused
PONS_E
SOE_E
0
0
0
0
0
0
X
X
X
X
0
0
1
0
R/W
R/W
R/W
R/W
LENDIAN
Reserved
This register configures the operation of the GPIC.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
Reserved:
The Reserved bit must be set low for correct operation of the FREEDM-
32P672.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
118
PMC [ PMC-SIERRA, INC ]
