RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x024 : FREEDM-32P672 Master Performance Monitor Control
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TP2EN
TABRT2EN
RP2EN
RLENE2EN
RABRT2EN
RFCSE2EN
RSPE2EN
Unused
TP1EN
TABRT1EN
RP1EN
RLENE1EN
RABRT1EN
RFCSE1EN
RSPE1EN
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register configures the events that are accumulated in the two configurable
performance monitor counters in the PMON block.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
RSPE1EN:
The receive small packet error accumulate enable bit (RSPE1EN) enables
counting of minimum packet size violation events. When RSPE1EN is set
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
114
PMC [ PMC-SIERRA, INC ]
