RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
interrupts are disabled and may be polled to detect receive packet format
error events.
RFOVRE:
The receive FIFO overrun error interrupt enable bit (RFOVRE) enables
receive FIFO overrun error interrupts to the PCI host. When RFOVRE is set
high, attempts to write data into the logical FIFO of a channel when it is
already full will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit
remains valid when interrupts are disabled and may be polled to detect
receive FIFO overrun events.
RPQSFE:
The receive packet descriptor small buffer free queue cache read interrupt
enable bit (RPQSFE) enables receive packet descriptor small free queue
cache read interrupts to the PCI host. When RPQSFE is set high, reading a
programmable number of RPDR blocks from the RPDR Small Buffer Free
Queue will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RPQSFE is set low. However, the RPQSFI bit
remains valid when interrupts are disabled and may be polled to detect
RPDR small buffer free queue cache read events.
RPQLFE:
The receive packet descriptor large buffer free queue cache read interrupt
enable bit (RPQLFE) enables receive packet descriptor large free queue
cache read interrupts to the PCI host. When RPQLFE is set high, reading a
programmable number of RPDR blocks from the RPDR Large Buffer Free
Queue will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when RPQLFE is set low. However, the RPQLFI bit
remains valid when interrupts are disabled and may be polled to detect
RPDR large buffer free queue cache read events.
RPQRDYE:
The receive packet descriptor ready queue write interrupt enable bit
(RPQRDYE) enables receive packet descriptor ready queue write interrupts
to the PCI host. When RPQRDYE is set high, writing a programmable
number of RPDRs to the RPDR Ready Queue will cause an interrupt to be
generated on the PCIINTB output. Interrupts are masked when RPQRDYE is
set low. However, the RPQRDYI bit remains valid when interrupts are
disabled and may be polled to detect RPDR ready queue write events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
93
PMC [ PMC-SIERRA, INC ]
