RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
RPDFQEE:
The receive packet descriptor free queue error interrupt enable bit
(RPDFQEE) enables receive packet descriptor free queue error interrupts to
the PCI host. When RPDFQEE is set high, attempts to retrieve an RPDR
when both the large buffer and small buffer free queues are empty will cause
an interrupt to be generated on the PCIINTB output. Interrupts are masked
when RPDFQEE is set low. However, the RPDFQEI bit remains valid when
interrupts are disabled and may be polled to detect RPDR free queue empty
error events.
RPDRQEE:
The receive packet descriptor ready queue error interrupt enable bit
(RPDRQEE) enables receive packet descriptor ready queue error interrupts
to the PCI host. When RPDRQEE is set high, attempts to write an RPDR
when ready queue is ready full will cause an interrupt to be generated on the
PCIINTB output. Interrupts are masked when RPDRQEE is set low.
However, the RPDRQEI bit remains valid when interrupts are disabled and
may be polled to detect RPDR ready queue full error events.
TDQFE:
The transmit packet descriptor free queue write interrupt enable bit (TDQFE)
enables transmit packet descriptor free queue write interrupts to the PCI host.
When TDQFE is set high, writing a programmable number of TDRs to the
TDR Free Queue will cause an interrupt to be generated on the PCIINTB
output. Interrupts are masked when TDQFE is set low. However, the TDQFI
bit remains valid when interrupts are disabled and may be polled to detect
TDR free queue write events.
TDQRDYE:
The transmit descriptor ready queue cache read interrupt enable bit
(TDQRDYE) enables transmit descriptor ready queue cache read interrupts
to the PCI host. When TDQRDYE is set high, reading a programmable
number of TDRs from the TDR Ready Queue will cause an interrupt to be
generated on the PCIINTB output. Interrupts are masked when TDQRDYE is
set low. However, the TDQRDYI bit remains valid when interrupts are
disabled and may be polled to detect TDR ready queue cache read events.
TDFQEE:
The transmit descriptor free queue error interrupt enable bit (TDFQEE)
enables transmit descriptor free queue error interrupts to the PCI host. When
TDFQEE is set high, attempting to write to the transmit free queue while the
queue is full will cause an interrupt to be generated on the PCIINTB output.
Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
94
PMC [ PMC-SIERRA, INC ]
