RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
During clock 6, the target is still not ready so another wait state is added.
During clock 7, the target asserts TRDYB to indicate that it is ready to complete the transfer.
During clock 8, the target latches in the last word and negates TRDYB and DEVSELB, having
seen FRAMEB negated previously. The initiator negates IRDYB. All of the above signals shall be
driven to their inactive state in this clock cycle except for FRAMEB which shall be tri-stated.
Figure 29 – PCI Write Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
T
T
Address Data 1
Bus Cmd
Data 2
Data 3
AD[31:0]
C/BEB[3:0]
Byte En Byte En
Byte Enable
T
T
T
IRDYB
TRDYB
DEVSELB
The PCI Target Disconnect (Figure 30) illustrates the case when the target wants to prematurely
terminate the current cycle. Note, when the FREEDM-8 is the target, it never prematurely
terminates the current cycle.
A target can terminate the current cycle by asserting the STOPB signal to the initiator. Whether
data is transferred or not depends on the state of the ready signals at the time that the target
disconnects. If the FREEDM-8 is the initiator and the target terminates the current access, the
FREEDM-8 will retry the access after two PCI bus cycles.
During clock 1, an access is in progress.
During clock 2, the target indicates that it wishes to disconnect by asserting STOPB. Data may be
transferred depending on the state of the ready lines.
During clock 3, the initiator negates FRAMEB to signal the end of the cycle.
During clock 4, the target negates STOPB and DEVSELB in response to the FRAMEB signal
being negated.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
253
PMC [ PMC-SIERRA, INC ]
