RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
The PCI Exclusive Lock Cycle Diagram (Figure 34) illustrates the case when the current initiator
locks the PCI bus. The FREEDM-8 will never initiate an lock, but will behave appropriately when
acting as a target.
During clock 1, the present initiator has gained access of the LOCKB signal and the PCI bus. The
first cycle of a locked access must be a read cycle. The initiator asserts FRAMEB and drives the
address of the target on the AD[31:0] lines.
During clock 2, the present initiator asserts LOCKB to indicate to the target that a locked cycle is
in progress.
During clock 3, the target samples the asserted LOCKB signal and marks itself locked. The data
cycle has to complete in order for the lock to be maintained. If for some reason the cycle was
aborted, the initiator must negate LOCKB.
During clock 4, the data transfer completes and the target is locked.
During clock 6, another initiator may use the PCI bus but it cannot use the LOCKB signal. If the
other initiator attempts to access the locked target that it did not lock, the target would reject the
access.
During clock 7, the same initiator that locked this target accesses the target. The initiator asserts
FRAMEB and negates LOCKB to re-establish the lock.
During clock 8, the target samples LOCKB deasserted and locks itself.
During clock 9, the initiator does not want to continue the lock so it negates LOCKB. The target
samples LOCKB and FRAMEB deasserted it removes its lock.
Figure 34 – PCI Exclusive Lock Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
T
T
T
FRAMEB
AD[31:0]
Address
T
Data
Address Data
LOCKB
IRDYB
T
T
T
T
T
T
TRDYB
DEVSELB
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
256
PMC [ PMC-SIERRA, INC ]
