RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of a channelised
E1 link is shown in Figure 24. The receive data stream is an E1 frame with a singe framing byte
(F1 to F8 in Figure 24) followed by octet bound time-slots 1 to 31. RCLK[n] is held quiescent
during the framing byte. The RD[n] data bit (B1 of TS1) clocked in by the first rising edge of
RCLK[n] after the framing byte is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS31)
clocked in by the last rising edge of RLCLK[n] before the framing byte is the least significant bit of
time-slot 31. In Figure 24, the quiescent period is shown to be a low level on RCLK[n]. A high
level, effected by extending the high phase of bit B8 of time-slot TS31, is equally acceptable. In
channelised E1 mode, RCLK[n] can only be gapped during the framing byte. It must be active
continuously at 2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the
PROV bit in the corresponding word of the receive channel provision RAM in the RCAS block to
low.
Figure 24 – Channelised E1 Receive Link Timing
RCLK[n]
B8
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4
RD[n]
B6 B7
TS 31
F1 F2 F3 F4 F5 F6 F7 F8
FAS / NFAS
TS 1
TS 2
14.2 Transmit Link Output Timing
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of a
unchannelised link is shown in Figure 25. The transmit data is viewed as a contiguous serial
stream. There is no concept of time-slots in an unchannelised link. Every eight bits are grouped
together into a byte with arbitrary byte alignment. Octet data is transmitted from most significant
bit (B1 in Figure 25) and ending with the least significant bit (B8 in Figure 25). Bits are updated on
the falling edge of TCLK[n]. A transmit link may be stalled by holding the corresponding TCLK[n]
quiescent. In Figure 25, bits B5 and B2 are shown to be stalled for one cycle while bit B6 is
shown to be stalled for three cycles. In Figure 25, the quiescent period is shown to be a low level
on TCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also
acceptable. Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame boundaries.
Figure 25 – Unchannelised Transmit Link Timing
TCLK[n]
B1 B2 B3 B4 B5
B6
B7 B8 B1 B2
TD[n]
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of a channelised
T1 link is shown in Figure 26. The transmit data stream is a T1 frame with a single framing bit (F
in Figure 26) followed by octet bound time-slots 1 to 24. TCLK[n] is held quiescent during the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
249
PMC [ PMC-SIERRA, INC ]
