RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Figure 28 – PCI Read Cycle
1
2
3
4
5
6
7
8
9
PCICLK
T
FRAMEB
T
T
T
Address
Data 1
Data 2
Byte Enable
Data 3
AD[31:0]
Bus Cmd
T
C/BEB[3:0]
Byte Enable
Byte Enable
IRDYB
TRDYB
T
T
DEVSELB
A PCI burst write transaction is shown in Figure 29. The cycle is valid for target and initiator
accesses. The target is responsible for incrementing the address for the duration of the data
burst. The 'T' symbol stands for a turn around cycle. A turn around cycle is required on all signals
which can be driven by more than one agent.
During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the
address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command (in the
above example the command would indicate a burst write). The IRDYB, TRDYB and DEVSELB
signals are in turnaround mode (no agent is driving the signals for this clock cycle). This cycle on
the PCI bus is called the address phase.
During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving
the first data word. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write
data. IRDYB is driven active by the initiator to indicate it is ready to accept the data transfer. The
target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the
initiator that it is ready to accept the data. All subsequent cycles on the PCI bus are called data
phases.
During clock 3, the target latches in the first data word. The initiator starts to drive the next data
word onto the AD[31:0] lines.
During clock 4, the target latches in the second data word. Both the initiator and the target
indicate that they are not ready to transfer any more data by negating the ready lines.
During clock 5, the initiator is ready to transfer the next data word so it drives the AD[31:0] lines
with the third data word and asserts IRDYB. The initiator negates FRAMEB since this is the last
data phase of this cycle. The target is still not ready so a wait state shall be added.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
252
PMC [ PMC-SIERRA, INC ]
