RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Fast back-to-back transactions are used by an initiator to conduct two consecutive transactions on
the PCI bus without the required idle cycle between them. This can only occur if there is a
guarantee that there will be no contention between the initiator or targets involved in the two
transactions. In the first case, an initiator may perform fast back-to-back transactions if the first
transaction is a write and the second transaction is to the same target. All targets must be able to
decode the above transaction. In the second case, all of the targets on the PCI bus support fast
back-to-back transactions, as indicated in the PCI Status configuration register. The FREEDM-8
only supports the first type of fast back-to-back transactions and is shown in Figure 35.
During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the
address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command. In this
example the command would indicate a single write. The IRDYB, TRDYB and DEVSELB signals
are in turnaround mode and are not being driven for this clock cycle. This cycle on the PCI bus is
called the address phase.
During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving
the data element. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write
data. IRDYB is driven active by the initiator to indicate that the data is valid.
The initiator negates FRAMEB since this the last data phase of this cycle. The target claims the
transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready
to accept the data.
During clock 3, the target latches in the data element and negates TRDYB and DEVSELB, having
seen FRAMEB negated previously. The initiator negates IRDYB and drives FRAMEB to start the
next cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with
the write command. In this example the command would indicate a burst write.
During clock 4, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving
the first data element. The initiator also drives the C/BEB[3:0] lines with the byte enables for the
write data. IRDYB is driven active by the initiator to indicate that the data is valid. The target
claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator
that it is ready to accept the data.
During clock 5, the initiator is ready to transfer the next data element so it drives the AD[31:0] lines
with the second data element. The initiator negates FRAMEB since this is the last data phase of
this cycle. The target accepts the first data element and negates TRDYB to indicate its is not
ready for the next data element.
During clock 6, the target is still not ready so a wait state shall be added.
During clock 7, the target asserts TRDYB to indicate that it is ready to complete the transfer.
During clock 8, the target latches in the last element and negates TRDYB and DEVSELB, having
seen FRAMEB negated previously. The initiator negates IRDYB. All of the above signals shall be
driven to their inactive state in this clock cycle, except for FRAMEB which shall be tri-stated. The
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
257
PMC [ PMC-SIERRA, INC ]
