RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
DFCS:
The diagnose frame check sequence bit (DFCS) controls the inversion of the FCS field
inserted into the transmit packet. The value of DFCS to be written to the channel provision
RAM, in an indirect channel write operation, must be set up in this register before triggering
the write. When DFCS is set to one, the FCS field in the outgoing HDLC stream is logically
inverted allowing diagnosis of downstream FCS verification logic. The outgoing FCS field is
not inverted when DFCS is set to zero. DFCS reflects the value written until the completion of
a subsequent indirect channel read operation.
INVERT:
The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the
outgoing HDLC stream. The value of INVERT to be written to the channel provision RAM, in
an indirect channel write operation, must be set up in this register before triggering the write.
When INVERT is set to one, the outgoing HDLC stream is logically inverted. The outgoing
HDLC stream is not inverted when INVERT is set to zero. INVERT reflects the value written
until the completion of a subsequent indirect channel read operation.
PRIORITYB:
The active low channel FIFO expedite enable bit (PRIORITYB) informs the partial packet
processor of the priority of the channel relative to other channels when requesting data from
the DMA port. The value of PRIORITYB to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before triggering the write.
Channel FIFOs with PRIORITYB set to one are inhibited from making expedited requests for
data to the TMAC. When PRIORITYB is set to zero, both normal and expedited requests can
be made to the TMAC. Channels with HDLC data rate to FIFO size ratio that is significantly
lower than other channels should have PRIORITYB set to one. PRIORITYB reflects the value
written until the completion of a subsequent indirect channel read operation.
7BIT:
The least significant stuff enable bit (7BIT) configures the HDLC processor to stuff the least
significant bit of each octet in the corresponding transmit link (TD[n]). The value of 7BIT to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write. When 7BIT is set high, the least significant bit (last bit
of each octet transmitted) does not contain channel data and is forced to the value configured
by the BIT8 register bit. When 7BIT is set low, the entire octet contains valid data and BIT8 is
ignored. 7BIT reflects the value written until the completion of a subsequent indirect channel
read operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
178
PMC [ PMC-SIERRA, INC ]
