RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x388 : THDL Indirect Channel Data #2
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
7BIT
PRIORITYB
INVERT
DFCS
0
0
0
0
X
X
X
0
0
0
0
0
0
0
0
0
Unused
Unused
Unused
FLEN[8]
FLEN[7]
FLEN[6]
FLEN[5]
FLEN[4]
FLEN[3]
FLEN[2]
FLEN[1]
FLEN[0]
Bit 8
W
W
W
W
W
W
W
W
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains data to be inserted into the channel provision RAM in an indirect write
operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
FLEN[8:0]:
The indirect FIFO length (FLEN[8:0]) is the number of blocks, less one, that is provisioned to
the circular channel FIFO specified by the FPTR[8:0] block pointer. The FIFO length to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
177
PMC [ PMC-SIERRA, INC ]
