RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
specified by XFER[2:0], the partial packet processor will make a request for data to the TMAC
to retrieve the XFER[2:0] + 1 blocks of data. FIFO free space and transfer size are measured
in the number of 16-byte blocks. XFER[2:0] reflects the value written until the completion of a
subsequent indirect channel read operation.
To prevent lockup, the channel transfer size (XFER[2:0]) can be configured to be less than or
equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel
transfer size can be set, such that, the total number of blocks in the logical channel FIFO
minus the start transmission level is an integer multiple of the channel transfer size.
The case of a single block transfer size is a special. When BURSTEN is set high and
XFER[2:0] = 'b000, the transfer size is variable. The THDL will request the TMAC to transfer
as much data as there is free space in the FIFO, up to a maximum set by BURST[2:0].
FLAG[2:0]:
The flag insertion control (FLAG[2:0]) configures the minimum number of flags or bytes of idle
bits the HDLC processor inserts between HDLC packets. The value of FLAG[2:0] to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write. The minimum number of flags or bytes of idle (8 bits
of 1's) inserted between HDLC packets is shown in the table below. FLAG[2:0] reflects the
value written until the completion of a subsequent indirect channel read operation.
Table 25 – FLAG[2:0] Settings
FLAG[2:0]
Minimum Number of Flag/Idle Bytes
000
001
010
011
100
101
110
111
1 flag / 0 Idle byte
2 flags / 0 idle byte
4 flags / 2 idle bytes
8 flags / 6 idle bytes
16 flags / 14 idle bytes
32 flags / 30 idle bytes
64 flags / 62 idle bytes
128 flags / 126 idle bytes
LEVEL[3:0]:
The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the TRANS bit, configure
the various channel FIFO free space levels which trigger the HDLC processor to start
transmission of a HDLC packet as well as trigger the partial packet buffer to make DMA
request for data as shown in the following table. The channel FIFO trigger level to be written
to the channel provision RAM, in an indirect write operation, must be set up in this register
before triggering the write. LEVEL[3:0] reflects the value written until the completion of a
subsequent indirect channel read operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
180
PMC [ PMC-SIERRA, INC ]
