RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x384 : THDL Indirect Channel Data #1
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
PROV
CRC[1]
CRC[0]
IDLE
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
DELIN
Unused
Unused
FPTR[8]
FPTR[7]
FPTR[6]
FPTR[5]
FPTR[4]
FPTR[3]
FPTR[2]
FPTR[1]
FPTR[0]
Bit 8
W
W
W
W
W
W
W
W
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains data read from the channel provision RAM after an indirect channel read
operation or data to be inserted into the channel provision RAM in an indirect channel write
operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
FPTR[8:0]:
The indirect FIFO block pointer (FPTR[8:0]) informs the partial packet buffer processor the
circular linked list of blocks to use for a FIFO for the channel. The FIFO pointer to be written
to the channel provision RAM, in an indirect write operation, must be set up in this register
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
174