RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x38C : THDL Indirect Channel Data #3
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
TRANS
Unused
Unused
Unused
LEVEL[3]
LEVEL[2]
LEVEL[1]
LEVEL[0]
FLAG[2]
FLAG[1]
FLAG[0]
Unused[
Unused
XFER[2]
XFER[1]
XFER[0]
0
X
X
X
0
0
0
0
0
0
0
X
X
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
R/W
R/W
R/W
Bit 1
Bit 0
This register contains data read from the channel provision RAM after an indirect read operation
or data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
XFER[2:0]:
The indirect channel transfer size (XFER[2:0]) specifies the amount of data the partial packet
processor requests from the TMAC block. The channel transfer size to be written to the
channel provision RAM, in an indirect write operation, must be set up in this register before
triggering the write. When the channel FIFO free space reaches or exceeds the limit
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
179
PMC [ PMC-SIERRA, INC ]
