RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
low, receive link #n is unchannelised. The E1 register bit is ignored. RCLK[n] is gapped
during non-data bytes. The choice between treating all data bits as a contiguous stream with
arbitrary byte alignment or byte aligned to gaps in RCLK[n] is controlled by the BSYNC bit.
E1:
The E1 frame structure select bit (E1) configures the corresponding receive link for
channelised E1 operation when CEN is set high. RCLK[n] is held quiescent during the FAS
and NFAS framing bytes. The data bit on RD[n] associated with the first rising edge of
RCLK[n] after an extended quiescent period is considered to be the most significant bit of
time-slot 1. Link data is present at time-slots 1 to 31. When E1 is set low and CEN is set
high, the corresponding receive link is configured for channelised T1 operation. RCLK[n] is
held quiescent during the framing bit. The data bit on RD[n] associated with the first rising
edge of RCLK[n] after an extended quiescent period is considered to be the most significant
bit of time-slot 1. Link data is present at time-slots 1 to 24. E1 is ignored when CEN is set
low.
BSYNC:
The byte synchronisation enable bit (BSYNC) controls the interpretation of gaps in RCLK[n]
when the corresponding link is in unchannelised mode (CEN set low). When BSYNC is set
high, the data bit on RD[n] clocked in by the first rising edge of RCLK[n] after an extended
quiescent period is considered to be the most significant bit of a data byte. When BSYNC is
set low, gaps in RCLK[n] carry no special significance. BSYNC is ignore when CEN is set
high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
112
PMC [ PMC-SIERRA, INC ]
