RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x180 : RCAS Link #0 Configuration
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
BSYNC
E1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
R/W
R/W
R/W
Bit 1
0
Bit 0
CEN
0
This register configures operational modes of receive link #0 (RD[0] / RCLK[0]).
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
CEN:
The channelise enable bit (CEN) configures receive link #0 for channelised operation.
RCLK[0] is held quiescent during the T1 framing bit and during the E1 framing bytes. The
data bit on RD[0] clocked in by the first rising edge of RCLK[0] after an extended quiescent
period is considered to be the most significant bit of time-slot 1. When CEN is set low,
receive link #0 is unchannelised. The E1 register bit is ignored. RCLK[0] is gapped during
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
109
PMC [ PMC-SIERRA, INC ]
