RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
gapped during non-data bytes. All data bits are treated as a contiguous stream with arbitrary
byte alignment.
E1:
The E1 frame structure select bit (E1) configures receive link #3 for channelised E1 operation
when CEN is set high. RCLK[3] is held quiescent during the FAS and NFAS framing bytes.
The data bit on RD[3] clocked in by the first rising edge of RCLK[3] after an extended
quiescent period is considered to be the most significant bit of time-slot 1. Link data is
present at time-slots 1 to 31. When E1 is set low and CEN is set high, receive link #3 is
configured for channelised T1 operation. RCLK[3] is held quiescent during the framing bit.
The data bit on RD[3] clocked in by the first rising edge of RCLK[3] after an extended
quiescent period is considered to be the most significant bit of time-slot 1. Link data is
present at time-slots 1 to 24. E1 is ignored when CEN is set low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
114
PMC [ PMC-SIERRA, INC ]
